Scopezero

🕐 Hour 1–3: Locking the Vision + AD9280 Datasheet Deep Dive

Settled on the core idea—a no-nonsense, open-source oscilloscope. Goal: capture analog signals at 100 MS/s using the Analog Devices AD9280 8-bit ADC.

Spent these hours buried in the AD9280 datasheet:

• Analog input:
  • Needs biasing around mid-supply (1.5 V typical).
  • Planned to use AC coupling with a bias network.
• Clocking:
  • Requires a clean 100 MHz input clock.
  • Not using MCU-generated clocks—went with a dedicated XO for stability.
• Digital interface:
  • 8-bit parallel output, sampled on rising edge of CLK.
  • No FIFO or latency—it just spews bits.
• Voltage compatibility:
  • Operates on 3.0–3.6 V analog/digital rails, perfect for a 3.3 V system.
• Pin strategy:
  • Tagged OTR, MODE, STBY, REFSENSE, REFTF, REFB, and DNC for proper handling.
  • Planned:
  • Pulling STBY low (keep it on)
  • REFB decoupled (recommended by datasheet)
  • Unused outputs marked NC in schematic

📝 Made notes and annotated diagrams to avoid referencing the datasheet 10 times per hour later.

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🕓 Hour 4–6: Microcontroller Switcheroo — Choosing ESP32-S3

Originally picked the RP2040, but ran into a wall:

• No real parallel interface for high-speed ADC.
• Could’ve used PIO, but not reliable for sustained 100 MS/s with 8-bit input.

So, switched to ESP32-S3-WROOM, which saved the day:

• Supports parallel camera input (I2S mode with DMA).
• Has plenty of GPIOs for 8-bit data + clock + I2C + control.
• Built-in USB = no extra FTDI headache.

Pin Plan:

Function	GPIO
D0–D7 (ADC)	GPIO10–17
PCLK (ADC CLK)	GPIO18
SDA	GPIO8
SCL	GPIO9
Buzzer	GPIO19 (later moved for conflict avoidance)

🎯 Sketched a block diagram and I/O mapping spreadsheet for sanity.

Spent time checking: - Bootstrapping pins (e.g., GPIO0, GPIO2) - Avoided using strapping pins for data lines - Prepped for I2C pull-ups, button GPIOs, and buzzer control with solder jumper

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🕖 Hour 7–10: Schematic Design in EasyEDA

Opened up EasyEDA and got serious.

ESP32-S3-WROOM

• Dropped in the module from LCSC library
• Wired power rails, caps (10uF + 0.1uF), and USB D+/D- for native USB

AD9280

• Had to create a custom symbol and footprint in EasyEDA:
  • 28-pin SSOP footprint (double-checked dimensions)
  • Annotated all pins: analog, digital, ref, and NCs

Power Management

• All operating at 3.3 V
• Decoupling caps on:
  • Every power pin (0.1uF near, 10uF bulk)
  • REFB, AVDD, DVDD, etc.

I2C OLED (128x64)

• Classic SSD1306 module
• SDA/SCL to GPIO8/9
• Added 4.7k pull-ups to 3.3V

Buzzer

• Wired buzzer to GPIO18
• Added a solder jumper to disable it if it gets annoying

Notes:

• Added labels and nets to every GPIO and signal for traceability
• Flagged unused pins (NC) in schematic to prevent floating
• Added a 3-pin header for external 100 MHz clock oscillator input (and optionally solder a small XO directly)

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🕚 Hour 11–14: ERC Madness and Clean-Up

Ran Electrical Rule Check (ERC)… got wrecked by red warnings.

Systematically fixed:

• Unused pins on ADC marked NC or tied appropriately:
  • OTR, DNC → NC
  • MODE, STBY → GND
  • REFSENSE → GND for internal reference
  • REFB, REFTF → Decoupled to GND
• Ensured every power pin had:
  • Proper decoupling
  • Clear net naming
  • No broken connections

Also:

• Rotated symbols to align pins logically
• Routed power to star topologies where needed
• Tidied up schematics so it wasn’t a spaghetti bowl

✅ Passed ERC with only cosmetic warnings remaining

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🕒 Hour 15–18: PCB Layout Time (EasyEDA PCB Mode)

Switched to PCB design view:

Layout Goals:

• Keep ADC and ESP32 as close as possible
• Minimize trace length on 100 MS/s digital signals
• Short, wide traces for D0–D7 and PCLK
• Separate analog and digital zones

Process:

• Placed decoupling caps right next to their pins
• Created ground plane on bottom layer
• Used vias to connect cap grounds directly to plane
• Routed I2C, buzzer, and USB away from ADC traces

Placement:

• ESP32 on one side, with USB connector near edge
• ADC on opposite side, input close to analog header
• Left room for future probes or front panel

✨ Left silkscreen notes like SDA, ADC D0, TRIGGER, etc. for debugging

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🕘 Hour 19–20: Visual Checks, 3D Render & Export

Final steps in EasyEDA:

• Used 2D and 3D views to ensure:
  • No overlapping footprints
  • No floating pads
  • Proper part clearance
• Snapped 3D render for documentation
• Exported:
  • Gerbers
  • BOM
  • Pick-and-Place
  • PDF schematic